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Saving Moore’s Law

Posted By Graphene Council, Tuesday, December 31, 2019
It’s a well-known observation: The number of transistors on a microchip will double roughly every two years. And, thanks to advances in miniaturization and performance, this axiom, known as Moore’s Law, has held true since 1965, when Intel co-founder Gordon Moore first made that statement based on emerging trends in chip manufacturing at Intel. 

However, integrated circuits are hitting hard physical limits that are rendering Moore’s Law obsolete — elements on a dense integrated circuit (IC) can get only so small and so tightly packed together before they begin to interfere with each other and otherwise lose their functionality.

“Apart from fundamental physical limits to the scaling of transistor feature sizes below a few nanometers, there are significant challenges in terms of reducing power dissipation, as well as justifying the incurred cost of IC fabrication,” said Kaustav Banerjee, a professor of electrical and computer engineering at UC Santa Barbara. As a result, the very devices that we rely on for their steadily improving performance and versatility — computers, smartphones, internet-enabled gadgets — would also hit a limit, he said.

But according to Banerjee, one of world’s leading scientific minds in the field of nanoelectronics, there is a way to maintain Moore’s Law indefinitely, by taking advantage of relatively new and promising two-dimensional (2D) materials and combining them with monolithic 3D (M3D) integration practices to create ultra-compact, yet high-performing electronic chips that could overcome the challenges that face conventional integrated circuits. While Banerjee first disclosed this idea in a visionary article back in 2014, more detailed research evaluating this technology from his Nanoelectronics Research Lab was recently published in the IEEE Journal of the Electron Devices Society.

“Two-dimensional materials can be stable in their monolayer form with atomic scale thickness – 0.5 nanometer or 5 Angstroms for graphene (a conductor) and hexagonal-boron-nitride (an insulator), and ~6.5 Angstroms for 2D transition metal dichalcogenides (semiconductors) such as molybdenum-disulphide (MoS2) or tungsten-disulphide/diselenide (WS2/WSe2).” Banerjee said. “In addition, due to their layered nature, they offer pristine surfaces relatively free of defects and are excellent conductors of heat in the in-plane direction. All these properties, along with the possibility to directly synthesize these materials on top of prefabricated devices, offer unprecedented advantages over conventional 3D ICs that are already in the market or M3D integration with conventional electronic materials.”

The Benefits of Thinness 

According to the Banerjee Group’s study, there’s a limit to how thin conventional semiconductor materials can get before their desirable electronic properties begin to fade. 

“Thickness scaling of common semiconductor materials, such as Si, becomes challenging below a few nanometers due to rapid degradation of their mobility caused by the increase in electron scatterings from surface roughness,” Banerjee said. “In fact, below ~1 nm, conventional materials like Si or Ge may not be thermodynamically stable.”

On the other hand, atomically thin and stable 2D materials, such as graphene, hexagonal boron nitride (h-BN), and transitional metal dichalcogenides (MoS2, WS2, WSe2, etc) are highly space-efficient, thickness-wise. Moreover, due to their layered nature and pristine interfaces, the 2D semiconductors exhibit reasonably high mobilities and immunity against surface defects, according to the paper. In addition, 2D materials tend to be a lot more flexible than their conventional counterparts, which make them ideal for state-of-the-art electronics applications, such as flexible displays.  Stacked 2D materials, in contrast to their stacked 3D counterparts, meanwhile, can also minimize the inter-tier signal delays, thermal resistance, and reduce potential overheating.

By selecting certain 2D materials and stacking them, according to the researchers, not only does the monolithic 3D conserve precious space on the chip, but also allows for configuration based on the combined electronic properties of the materials.

For example, owing to the atomically-thin vertical dimensions of 2D materials, and carefully-designed inter-tier electrostatics with graphene shielding layer that also benefits from enhanced heat dissipation, aggressive scaling of tier thickness down to sub-μm can be achieved,” Banerjee said. “Such scaling allows over 10-folds higher integration density with respect to conventional 3D integration, and over 150% greater integration density with respect to conventional M3D integration, with plenty of room for further improvements.” 

“Thus, 2D materials can help realize the ultimate density scaling of integrated electronics — both laterally and vertically — which can usher an unprecedented era of innovation and economic growth for the worldwide semiconductor industry,” he added.

Manufacturing Outlook

As with many innovations with potential to become mainstream technologies, there are challenges to consider to pave the way toward their mass manufacturing. For monolithic 3D devices, the challenges are to be able to fabricate these components at relatively low temperatures (lower than 500 degrees Celsius) to avoid degradations and damages to prefabricated devices located in the lower tiers; electromagnetic interference; and heat dissipation.

Last year, Banerjee’s group demonstrated a CMOS compatible graphene synthesis method that essentially addressed the low-temperature and transfer-free synthesis challenge for graphene. Similar efforts are underway in his laboratory to synthesize other 2D materials directly on wafers at low temperatures.

“Additionally, careful design is needed to electrically shield the generated electromagnetic waves from affecting the operations of devices on adjacent or nearby tiers,” said Junkai Jiang, the lead author of the article and recent recipient of a doctoral degree in electrical and computer engineering from Banerjee’s laboratory. The researchers noted that by using a thin graphene shielding layer between tiers (preferably doped to enhance electromagnetic screening effect), interference can be prevented even as the vertical layers are scaled down. 

In terms of heat dissipation, the thinness of the material itself is conducive to allowing the heat from densely packed stacked components to dissipate efficiently. Kamyar Parto, a co-author of the study and a member of Banerjee’s lab, remarked that “the 2D materials have much higher in-plane thermal conductivity compared to thinned-down conventional materials like silicon, which helps fast lateral heat transport, thereby reducing the risks of any hot-spot formation.”  

“Ultimately, we envision heterogeneously integrated devices and technologies enabled by 2D materials to realize the world’s tallest and densest ‘chip-cities’ with unprecedented performance, storage capacity, and energy-efficiency,” he added.

Tags:  2D materials  Electronics  Graphene  Hexagonal boron nitride  Intel  Junkai Jiang  Kamyar Parto  Kaustav Banerjee  nanoelectronics  Semiconductor 

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Graphene in Electronic Circuits

Posted By Graphene Council, Wednesday, July 31, 2019
Updated: Tuesday, July 30, 2019
Ever since graphene was discovered in 2004, researchers around the world have been working to develop commercially scalable applications for this high-performance material.

Graphene is 100 to 300 times stronger than steel at the atomic level and has a maximum electrical current density orders of magnitude greater than that of copper, making it the strongest, thinnest and, by far, the most reliable electrically conductive material on the planet. It is, therefore, an extremely promising material for interconnects, the fundamental components that connect billions of transistors on microchips in computers and other electronic devices in the modern world.

For over two decades, interconnects have been made of copper, but that metal encounters fundamental physical limitations as electrical components that incorporate it shrink to the nanoscale. “As you reduce the dimensions of copper wires, their resistivity shoots up,” said Kaustav Banerjee, a professor in the Department of Electrical and Computer Engineering. “Resistivity is a material property that is not supposed to change, but at the nanoscale, all properties change.”

As the resistivity increases, copper wires generate more heat, reducing their current-carrying capacity. It’s a problem that poses a fundamental threat to the $500 billion semiconductor industry. Graphene has the potential to solve that and other issues. One major obstacle, though, is designing graphene micro-components that can be manufactured on-chip, on a large scale, in a commercial foundry.

“Whatever the component, be it inductors, interconnects, antennas or anything else you want to do with graphene, industry will move forward with it only if you find a way to synthesize graphene directly onto silicon wafers,” Banerjee said. He explained that all manufacturing processes related to the transistors, which are made first, are referred to as the ‘front end.’ To synthesize something at the back-end — that is, after the transistors are fabricated — you face a tight thermal budget that cannot exceed a temperature of about 500 degrees Celsius. If the silicon wafer gets too hot during the back-end processes employed to fabricate the interconnects, other elements that are already on the chip may get damaged, or some impurities may start diffusing, changing the characteristics of the transistors.

Now, after a decade-long quest to achieve graphene interconnects, Banerjee’s lab has developed a method to implement high-conductivity, nanometer-scale doped multilayer graphene (DMG) interconnects that are compatible with high-volume manufacturing of integrated circuits. A paper describing the novel process was named one of the top papers at the 2018 IEEE International Electron Devices Meeting (IEDM),  from more than 230 that were accepted for oral presentations. It also was one of only two papers included in the first annual “IEDM Highlights” section of an issue of the journal Nature Electronics.

Banerjee first proposed the idea of using doped multi-layer graphene at the 2008 IEDM conference and has been working on it ever since. In February 2017 he led the experimental realization of the idea by Chemical Vapor Deposition (CVD) of multilayer graphene at a high temperature, subsequently transferring it to a silicon chip, then patterning the multilayer graphene, followed by doping. Electrical characterization of the conductivity of DMG interconnects down to a width of 20 nanometers established the efficacy of the idea that was proposed in 2008. However, the process was not “CMOS-compatible” (the standard industrial-scale process for making integrated circuits), since the temperature of CVD processes far exceed the thermal budget of back-end processes.

To overcome this bottleneck, Banerjee’s team developed a unique pressure-assisted solid-phase diffusion method for directly synthesizing a large area of high-quality multilayer graphene on a typical dielectric substrate used in the back-end CMOS process. Solid-phase diffusion, well known in the field of metallurgy and often used to form alloys, involves applying pressure and temperature to two different materials that are in close contact so that they diffuse into each other.

Banerjee’s group employed the technique in a novel way. They began by depositing solid-phase carbon in the form of graphite powder onto a deposited layer of nickel metal of optimized thickness. Then they applied heat (300 degrees Celsius) and nominal pressure to the graphite powder to help break down the graphite. The high diffusivity of carbon in nickel allows it to pass rapidly through the metal film.

How much carbon flows through the nickel depends on its thickness and the number of grains it holds. “Grains” refer to the fact that deposited nickel is not a single-crystal metal, but rather a polycrystalline metal, meaning it has areas where two single-crystalline regions meet each other without being perfectly aligned. These areas are called grain boundaries, and external particles — in this case, the carbon atoms — easily diffuse through them. The carbon atoms then recombine on the other surface of the nickel closer to the dielectric substrate, forming multiple graphene layers.

Banerjee’s group is able to control the process conditions to produce graphene of optimal thickness. “For interconnect applications, we know how many layers of graphene are needed,” said Junkai Jiang, a Ph.D. candidate in Banerjee’s lab and lead author of the 2018 IEDM paper. “So we optimized the nickel thickness and other process parameters to obtain precisely the number of graphene layers we want at the dielectric surface. “Subsequently, we simply remove the nickel by etching so that what’s left is only very high-quality graphene — virtually the same quality as graphene grown by CVD at very high temperatures,” he continued. “Because our process involves relatively low temperatures that pose no threat to the other fabricated elements on the chip, including the transistors, we can make the interconnects right on top of them.”

UCSB has filed a provisional patent on the process, which overcomes the obstacles that, until now, have prevented graphene from replacing copper. Bottom line: graphene interconnects help to create faster, smaller, lighter, more flexible, more reliable and more cost-effective integrated circuits. Banerjee is currently in talks with industry partners interested in potentially licensing this CMOS-compatible graphene synthesis technology, which could pave the way for what would be the first 2D material to enter the mainstream semiconductor industry.

Tags:  2D materials  CVD  Graphene  Graphite  Junkai Jiang  Kaustav Banerjee  Semiconductor  UC Santa Barbara 

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